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ET74LVC1G79
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General Description
The ET74LVC1G79 is a single positive edge triggered D-type flip-flop, Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in mixed 3.3V and 5V environments. Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging back-flow current through the device when it is powered down.
Specification
Sample
Features
- Wide Supply Voltage Range from 1.65V to 5.5V
- Over Voltage Tolerant Inputs to 5.5V
- High Noise Immunity
- ±24mA Output Drive (VCC = 3.0V)
- CMOS Low Power Consumption
- Direct Interface with TTL Levels
- IOFF Circuitry Provides Partial Power-down Mode Operation
- Latch-up Performance Exceeds 200mA per JESD78, Class II
Technical Documentation
| Type | Title | Format | Date |
|---|---|---|---|
| Datasheet | ET74LVC1G79 Datasheet | 2025-11-07 |
