ET74HC138/238

General Description

74HC138 is a high speed CMOS decoder circuit, it accepts a three bit binary weighed address on input pins A0, A1, A2 and when enabled will produce one active low output and other seven output high level. In addition, the circuit has two low-level enable pins E1 and E2 and high-level enable pin E3. When the circuit is in the non enable state, all output pins output high level; When the circuit is enabled, E1 and E2 are low level and E3 is high level. The circuit uses multiple enable signals to realize the expansion of the decoder. Without using additional devices, it can be expanded into a 4 to 16 decoder, while expanding 5 to 32 decoding requires an inverter.

Specification Sample