EN
ET74LVC1G80
연락처
일반 설명
The ET74LVC1G80 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and its complement will appear at the Q output. Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall time. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging back-flow current through the device when it is powered down.
사양
샘플
특징
- Wide Supply Voltage Range from 1.65V to 5.5V
- Over Voltage Tolerant Inputs to 5.5V
- High Noise Immunity
- ±24mA Output Drive (VCC = 3.0V)
- CMOS Low Power Consumption
- Direct Interface with TTL Levels
- IOFF Circuitry Provides Partial Power-down Mode Operation
- Latch-up Performance Exceeds 200mA per JESD78, Class II
기술 문서
| 유형 | 제목 | 형식 | 날짜 |
|---|---|---|---|
| 데이터시트 | ET74LVC1G80 데이터시트 | 2026-04-16 |
