ET74LVC1G80

Description générale

The ET74LVC1G80 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and its complement will appear at the Q output. Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall time. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging back-flow current through the device when it is powered down.

Spécifications

Échantillon

Caractéristiques

Wide Supply Voltage Range from 1.65V to 5.5V
Over Voltage Tolerant Inputs to 5.5V
High Noise Immunity
±24mA Output Drive (VCC = 3.0V)
CMOS Low Power Consumption
Direct Interface with TTL Levels
IOFF Circuitry Provides Partial Power-down Mode Operation
Latch-up Performance Exceeds 200mA per JESD78, Class II

Documentation technique

Type	Titre	Format	Date
Fiche technique	ET74LVC1G80 Fiche technique	PDF (EN ANGLAIS)	2026-04-16

Applications

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Échantillons